Project - Design of Integrated Systems (WS)

Format

The practical and teaching session will be held in presence until further notice. If regulations change during the course or if too many students want to participate, it will be continued online. Please register to the Moodle course to get more and the latest information and to allow use to plan the course.

Content

The objective of the course is to deepen participants' knowledge of VLSI system design by developing a small integrated circuit. Theoretical knowledge covering the design flow for integrated digital circuits for programmable logic is taught in introductory lectures, supplemented by practical exercises and an interactive online tutorial.

In the following practical part of the course, the participants will use the learned knowledge in an exemplary project. Based on a given specification, a system design has to be created and presented. The design will be implemented in Verilog as a hierarchical model, which will then be simulated as RTL using the software Vivado from Xilinx. Subsequently, the modeled design will be synthesized to netlists and routed, using the synthesis and implementations tools of Vivado. Further simulations on the logic cell level including timing analysis will be used to verify the correct functionality of the design. Finally, the design will be tested on an FPGA.

The first five lessons will be lectures with a fixed schedule, two additional lab exercises and an interactive online tutorial, available on the institute web page. Attendance at all tuition lessons and a successful completion of the online tutorial is mandatory for passing the project.

Upon that, each student team can use the time at the tuition lessons to get on with their project in their own speed. Part of the learning-experience is a self-control of your progress with respect to given project milestones. At the usual lab times, the help of the tutors are available to help with problems and questions. A detailed schedule including mandatory milestones will be handed out in the first lecture.

The course is open for anybody studying Communications Technology (CT).

The number of participants for the course is limited. Students in a masters program of Electrical Engineering (ET) and Communications and Computer Engineering (IST) with a sufficient understanding of the english language can participate, if there are free places. Provisionally registrations in the bachelor course can be considered in case that the master course at the University of Ulm starts with the current Semester.

For the online registration the matriculation number, the ulub number and the course of studies is needed. The practical part of the project is done in groups of two, the name of the desired team partner can be given.

The registration (see Moodle Course) for the course starts on the the first day of the semester and ends one day before the first lecture. The script for the course can be ordered at the printing system of the Fachschaft (druck.fs-et.de).

There will be no notification if you are accepted for the course or have to wait for the next semester. This decision will be announced during the first lab course.
Students who do not appear or arrive delayed (see right column) to the first meeting can not be considered for the course.

• Interactive Verilog Online-Tutorial
• ZYBO Reference Manual (PDF)
• Zynq-7000 AP SoC Overview (PDF)
• Verilog Language Reference (PDF)
• Verilog Examples & Additional Tutorials

• Daniel D. Gajski, “Principles of Digital Design”
• Ken Coffman, "Real World FPGA Design with Verilog"
• Donald E. Thomas & Philips R. Moorby, "The Verilog Hardware Description Language"