M.Sc. Paul Kässer
Paul Kässer studied Electrical Engineering at the University of Ulm where he received his B.Sc. degree in 2018 and his M.Sc. in 2021. The topic of his Master thesis was ''Development and Test of a Mixed-Signal Neural-Network Processing-Element''.
During his bachelor studies, he did an internship in India at TVS Motor Company in control engineering, where he built a motion-controlled robot arm. At the end of his master studies, he pursued another internship at Qualcomm, where he was working in the field of Custom Design Automation.
Since September 2021 he is working as research assistant towards the Ph.D. degree under the supervision of Prof. Dr.-Ing Maurits Ortmanns. His research area is the system-level modeling and optimization of Sigma-Delta ADCs.
Projekte
Online Tool for Rapid Continuous-Time ΣΔ Modulator Design
P. Kässer: ΣΔ A/D converters are the state of the art for many different applications. The basis for this type of A/D converter is the ΣΔ modulator. For a long time, discrete-time (DT) ΣΔ modulators dominated as their design techniques could easily be adopted to ensured high performance... [ more]
Studentische Arbeiten
[mt] = Masterarbeit, [rp] = Bachelorarbeit
Aktuelle Arbeiten
Abgeschlossene Arbeiten
- Qiuyang Zhang
Development and Test of a Reliable Capacitance-to-Digital Converter for PUF Readouts [mt]
Publikationen
2024
Offset Cancellation in Incremental ∆Σ ADCs
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
Mai 2024
DOI: | 10.1109/ISCAS58744.2024.10557952 |
Stability Prediction of Δ∑ Modulators using Artificial Neural Networks
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
Mai 2024
DOI: | 10.1109/ISCAS58744.2024.10557868 |
Inner Transfer Functions in Incremental ΔΣ ADCs
IEEE Transactions on Circuits and Systems II: Express Briefs
April 2024
DOI: | 10.1109/TCSII.2024.3390397 |
Non-Ideal Reset in Incremental Delta-Sigma ADCs
IEEE 22nd Interregional NEWCAS Conference Sherbrooke, Quebec, Canada
April 2024
DAC Element Mismatch Shaping Algorithms in Incremental Delta-Sigma ADCs
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
Januar 2024
DOI: | 10.1109/ISCAS58744.2024.10558337 |
2023
Quantizer Gain in Incremental Delta-Sigma ADCs
30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, pp. 1-4
Dezember 2023
DOI: | 10.1109/ICECS58634.2023.10382904 |
A Feasibility Study on a Switched-Capacitor Based PUF in 28 nm Technology
30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye
Dezember 2023
DOI: | 10.1109/ICECS58634.2023.10382899 |
Optimum Position of Digital DAC Error Correction relative to the Decimation Filter in ΔΣ ADCs
30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye
Dezember 2023
DOI: | 10.1109/ICECS58634.2023.10382885 |
Frequency-Domain Analysis of Reconfigured Incremental ΔΣ ADCs on the Example of the Exponential Phase
IEEE Transactions on Circuits and Systems I: Regular Papers
September 2023
DOI: | 10.1109/TCSI.2023.3310655 |
Linear-Exponential I-DS ADCs: Analysis, Limitations and Higher Order
IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, pp. 1-5
Mai 2023
DOI: | 10.1109/ISCAS46773.2023.10182215 |
2021
Nonlinearity Modeling for Mixed-Signal Inference Accelerators in Training Frameworks
28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 1-4
2021
DOI: | 10.1109/ICECS53924.2021.9665503 |