Fully Programmable LDPC Decoder
Data transmission over a noisy channel implies signal distortion and possibly the corruption of the received data. To correct these transmission errors, error correcting coding is needed. In the 90ties, Low-Density Parity-Check codes were rediscovered which allow a transmission within a fraction of a dB from the Shannon limit.
LDPC codes can be defined by a bipartite graph. The belief propagation decoding algorithm is based on message passing between check and variable nodes in the graph. After a certain number of iterations or as soon as a valid codeword is detected, decoding is stopped. The main challenge in decoder implementation lies in the random interconnection network between check and variable nodes.
In our research we develop partly-parallel hardware implementations for fully programmable LDPC decoders. To solve the complex interconnection problem, different heuristic and deterministic mapping and scheduling algorithms have been developed. While most currently published decoder designs are restricted to one single code or a structured code ensemble, we focus on fully programmable decoder architectures that allow decoding of quasi-cyclic, protograph and any other structured or unstructured LDPC code with the identical hardware. Code design is therefore no longer constrained by the decoder architecture and LDPC codes can be chosen according to optimum error correction performance. Furthermore, this approach allows the implementation of multi-standard decoders.