Ultra-low Power, Wide Bandwidth Continuous-time Delta Sigma Analog to Digital Converter Design
Continuous-time delta sigma modulators (CTDSMs) have recently become the key device for broadband wireless and wireline communication. Due to their built in anti-aliasing filter and the ability to have relaxed sampling requirements the CTDS modulators are preferred over their discrete time counterparts.
This project focuses on designing, developing and testing very high speed, wide bandwidth, low power sigma delta ADCs. One of the key techniques to reaching this goal is by designing the loop filter with highly reduced gain bandwidth product (GBW) amplifiers to drastically reduce the power and area while also pushing the overall sampling frequency of the ADC to the limit of the technology. With the ability of using multi-bit quantizers and lowering the Oversampling Ratio (OSR), bandwidths in the range of 20 to 50MHz in a 90nm CMOS process with resolutions of around 12 bits are very feasible. Applying compensation technique opens a feasible way to further increase the conversion rates of CT-SDM while keeping the FOM below 100fJ/conversion.