In our research we develop partly-parallel hardware implementations for fully programmable LDPC decoders. To solve the complex interconnection problem, different heuristic and deterministic mapping and scheduling algorithms have been developed. While most currently published decoder designs are restricted to one single code or a structured code ensemble, we focus on fully programmable decoder architectures that allow decoding of quasi-cyclic, protograph and any other structured or unstructured LDPC code with the identical hardware. Code design is therefore no longer constrained by the decoder architecture and LDPC codes can be chosen according to optimum error correction performance. Furthermore, this approach allows the implementation of multi-standard decoders.