Continuous-Time (CT) Analog-to-Digital Converters (ADCs) have become ubiquitous in state-of-the-art (SoA) communication systems thanks to their achievable conversion speed, resolution and power efficiency. Recently, CT pipelined ADCs have gained interest in the research community. In a pipelined ADC, the input signal is first digitized by a coarse quantizing stage. The resulting signal is converted back to the analog domain using a digital-to-analog converter (DAC) and subtracted from the input signal. The fine stage operates on the resulting residue signal, which ideally only contains the coarse stage’s quantization error. Due to the lowered signal power, an inter-stage gain (ISG) can be used, to suppress the fine stage’s errors caused by thermal noise, non-linearity and quantization error. In state-of-the-art (SoA) implementations, the coarse ADC is implemented by a Flash or successive-approximation register (SAR) quantizer. These implementations allow for a high conversion rate at low to medium resolution. Since CT pipelined ADCs employ oversampling, the fine stage is often realized as a noise-shaping architecture such as a CT Delta-Sigma Modulator (DSM). The architecture is then called 0-X MASH DSM, where X refers to the order of the DSM’s loop filter.

A main tradeoff in the design of a 0-X MASH DSM is the selection of the ISG: a higher ISG results in more suppression of fine stage errors, allowing for a higher resolution of the ADC. However, the ISG is limited by the coarse stage’s quantization noise and signal leakage caused by non-ideal cancellation when building the residue.
A further critical component is the coarse DAC, as its errors can not be cancelled by the noise cancellation logic. SoA implementations often use digital calibration and do not disclose the required effort in terms of power and die area.

In the first phase of this project, the suitability of a time-interleaved (TI) SAR ADC as coarse ADC in a 0-X MASH DSM was evaluated. A novel 6-bit, 2xTI SAR ADC was implemented in a 22nm FDSOI CMOS process. Furthermore, an intrinsically linear architecture for the coarse DAC employing a digital DSM (DDSM) was developed. With this, the coarse stage can be realized by a TI-SAR ADC and a single DAC, preventing any non-idealities caused by time-interleaving. Furthermore, the all-pass filter (APF) necessary for residue building and the ISG were investigated.

The second phase of the project focuses on the implementation of the full CT pipelined ADC comprising the TI SAR, the DDSM DAC and a fine stage DSM. Furthermore, a digital noise cancellation logic with reduced complexity will be developed.