Publications - Dr.-Ing. J. Becker
Papers
2025
106.
Mandry,
H.;
Driemeyer,
B.;
Becker,
J.;
Ortmanns,
M.
Investigation of the Influence of Multi-Valued Symbol Extraction on PUF Randomness
31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
January 2025
Investigation of the Influence of Multi-Valued Symbol Extraction on PUF Randomness
31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
January 2025
| DOI: | 10.1109/ICECS61496.2024.10849251 |
2024
105.
Driemeyer,
B.;
Mandry,
H.;
Wiens,
D.-P.;
Becker,
J.;
Ortmanns,
M.
Optimisation of RO-PUF Design Parameters for Minimising the Effective Area per PUF Bit
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
May 2024
Optimisation of RO-PUF Design Parameters for Minimising the Effective Area per PUF Bit
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
May 2024
| DOI: | 10.1109/ISCAS58744.2024.10558478 |
2023
104.
Sporer,
M.;
Graber,
N.;
Reich,
S.;
Gueli,
C.;
Becker,
J.;
Stieglitz,
T.;
Ortmanns,
M.
NeuroBus – Architecture and Communication Bus for an Ultra-Flexible Neural Interface
IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA
May 2023
NeuroBus – Architecture and Communication Bus for an Ultra-Flexible Neural Interface
IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA
May 2023
| DOI: | 10.1109/ISCAS46773.2023.10181816 |
2022
103.
Mokhtar,
M. A.;
Abdelaal,
A.;
Sporer,
M.;
Becker,
J.;
Kauffman,
J. G.;
Ortmanns,
M.
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
IEEE Journal of Solid-State Circuits, Volume: 57, Issue: 11
November 2022
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
IEEE Journal of Solid-State Circuits, Volume: 57, Issue: 11
November 2022
| DOI: | 10.1109/JSSC.2022.3160325 |
102.
Sporer,
M.;
Reich,
S.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
A Wireless Headstage Prototype Based on a Neurorecorder IC
IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan
October 2022
A Wireless Headstage Prototype Based on a Neurorecorder IC
IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan
October 2022
| DOI: | 10.1109/BioCAS54905.2022.9948554 |
101.
Driemeyer,
B.;
Mandry,
H.;
Wiens,
D.-P.;
Becker,
J.;
Ortmanns,
M.
PUF-Entropy Extraction of DAC Intersymbol-Interference using Continuous-Time Delta-Sigma ADCs
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
October 2022
PUF-Entropy Extraction of DAC Intersymbol-Interference using Continuous-Time Delta-Sigma ADCs
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
October 2022
| DOI: | 10.1109/ICECS202256217.2022.9971072 |
100.
Reich,
S.;
Sporer,
M.;
Becker,
J.;
Rieger,
S. B.;
Schüttler,
M.;
Ortmanns,
M.
A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking Capacitors
IEEE ESSDERC/ESSCIRC 2022, Milan, Italy
September 2022
A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking Capacitors
IEEE ESSDERC/ESSCIRC 2022, Milan, Italy
September 2022
2021
99.
Reich,
S.;
Sporer,
M.;
Haas,
M.;
Becker,
J.;
Schüttler,
M.;
Ortmanns,
M.
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip
IEEE Journal of Solid-State Circuits, vol. 56, issue 8, pp. 2476-2487
August 2021
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip
IEEE Journal of Solid-State Circuits, vol. 56, issue 8, pp. 2476-2487
August 2021
| DOI: | 10.1109/JSSC.2021.3076510 |
98.
Mandry,
H.;
Müelich,
S.;
Becker,
J.;
Fischer,
R.;
Ortmanns,
M.
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS)
May 2021
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS)
May 2021
| DOI: | 10.1109/ISCAS51556.2021.9401501 |
97.
Mokhtar,
M. A.;
Abdelaal,
A.;
Sporer,
M.;
Becker,
J.;
Kauffman,
J. G.;
Ortmanns,
M.
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s ContinuousTime Incremental Delta-Sigma ADC Utilizing Variable Bit-Width Quantizer in 28nm CMOS
IEEE Custom Integrated Circuits Conference (CICC), Texas, USA (Virtual)
April 2021
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s ContinuousTime Incremental Delta-Sigma ADC Utilizing Variable Bit-Width Quantizer in 28nm CMOS
IEEE Custom Integrated Circuits Conference (CICC), Texas, USA (Virtual)
April 2021
96.
Rajabzadeh,
M.;
Ungethüm,
J.;
Herkle,
A.;
Schilpp,
C.;
Becker,
J.;
Fauler,
M.;
Wittekindt,
O.;
Frick,
M.;
Ortmanns,
M.
A PCB Based 24-Ch. MEA-EIS Allowing Fast Measurement of TEER
IEEE Sensor Journal
March 2021
A PCB Based 24-Ch. MEA-EIS Allowing Fast Measurement of TEER
IEEE Sensor Journal
March 2021
| DOI: | 10.1109/JSEN.2021.3067823 |
2020
95.
Herkle,
A.;
Rossak,
P.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
Comparison of measurement and readout strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
Comparison of measurement and readout strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
94.
Herkle,
A.;
Mandry,
H.;
Becker,
J.;
Reich,
S.;
Sporer,
M.;
Ortmanns,
M.
Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
93.
Herkle,
A.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
Live Demonstration: Generating FPGA Fingerprints utilizing Full-Chip Characterization with Ring-Oscillator PUFs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
Live Demonstration: Generating FPGA Fingerprints utilizing Full-Chip Characterization with Ring-Oscillator PUFs
IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain
October 2020
92.
Rajabzadeh,
M.;
Häberle,
M.;
Becker,
J.;
Ortmanns,
M.
Comparison Study of DAC Realizations in Current Input CTΣΔ Modulators
IEEE Transactions on Circuits and Systems II: Express Briefs
July 2020
Comparison Study of DAC Realizations in Current Input CTΣΔ Modulators
IEEE Transactions on Circuits and Systems II: Express Briefs
July 2020
| DOI: | 10.1109/TCSII.2020.3007964 |
91.
Mandry,
H.;
Herkle,
A.;
Müelich,
S.;
Becker,
J.;
Fischer,
R.;
Ortmanns,
M.
Normalization and Multi-Valued Symbol Extraction from RO-PUFs for Enhanced Uniform Probability Distributions
IEEE Transactions on Circuits and Systems--II: Express Briefs
March 2020
Normalization and Multi-Valued Symbol Extraction from RO-PUFs for Enhanced Uniform Probability Distributions
IEEE Transactions on Circuits and Systems--II: Express Briefs
March 2020
| DOI: | 10.1109/TCSII.2020.2980748 |
2019
90.
Herkle,
A.;
Mandry,
H.;
Becker,
J.;
Ortmanns,
M.
In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, USA
May 2019
In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, USA
May 2019
| DOI: | 10.18725/OPARU-14107 |
89.
Mandry,
H.;
Herkle,
A.;
Kürzinger,
L.;
Müelich,
S.;
Becker,
J.;
Fischer,
R.;
Ortmanns,
M.
Modular PUF Coding Chain with High-Speed Reed-Muller Decoder
IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan
May 2019
Modular PUF Coding Chain with High-Speed Reed-Muller Decoder
IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan
May 2019
2018
88.
Lv,
L.;
Jain,
A.;
Zhou,
X.;
Becker,
J.;
Li,
Q.;
Ortmanns,
M.
A 0.4-V Gm–C Proportional-Integrator-Based Continuous-Time Delta-Sigma Modulator With 50-kHz BW and 74.4-dB SNDR
IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3256-3267
November 2018
A 0.4-V Gm–C Proportional-Integrator-Based Continuous-Time Delta-Sigma Modulator With 50-kHz BW and 74.4-dB SNDR
IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3256-3267
November 2018
87.
Herkle,
A.;
Becker,
J.;
Ortmanns,
M.
Methoden zur Verbesserung von CMOS integrierten Arbiter-PUFs
16. GMM/ITG-Fachtagung Analog, München, Germany
September 2018
Methoden zur Verbesserung von CMOS integrierten Arbiter-PUFs
16. GMM/ITG-Fachtagung Analog, München, Germany
September 2018
| DOI: | 10.18725/OPARU-17977 |
86.
Herkle,
A.;
Becker,
J.;
Ortmanns,
M.
An Arbiter PUF employing eye-opening oscillation for improved noise suppression
IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy
May 2018
An Arbiter PUF employing eye-opening oscillation for improved noise suppression
IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy
May 2018
| DOI: | 10.18725/OPARU-17954 |
85.
Rajabzadeh,
M.;
Djekic,
D.;
Häberle,
M.;
Becker,
J.;
Anders,
J.;
Ortmanns,
M.
Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT Σ∆ Modulator
IEEE International Symposium on Circuits & Systems (ISCAS), Florence, Italy
May 2018
Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT Σ∆ Modulator
IEEE International Symposium on Circuits & Systems (ISCAS), Florence, Italy
May 2018
84.
Chi,
J.;
Jain,
A.;
Sauerbrey,
J.;
Becker,
J.;
Ortmanns,
M.
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications
2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, pp. 1-4
May 2018
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications
2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, pp. 1-4
May 2018
83.
Lv,
L.;
Jain,
A.;
Zhou,
X.;
Becker,
J.;
Li,
Q.;
Ortmanns,
M.
A 0.4-VGm–CProportional-Integrator-Based Continuous-TimeΔΣModulator With 50-kHz BW and 74.4-dB SNDR
IEEE Journal of Solid-State Circuits, Volume: 53 , Issue: 11, Page s: 3256 - 3267
2018
A 0.4-VGm–CProportional-Integrator-Based Continuous-TimeΔΣModulator With 50-kHz BW and 74.4-dB SNDR
IEEE Journal of Solid-State Circuits, Volume: 53 , Issue: 11, Page s: 3256 - 3267
2018
82.
Al Marashli,
A.;
Anders,
J.;
Becker,
J.;
Ortmanns,
M.
A Nyquist rate SAR ADC employing incremental ΣΔ DAC achieving peak SFDR = 107 dB at 80 kS/s
IEEE Journal of Solid-State Circuits, Volume: 53, Issue: 5, Page s: 1493 - 1507
2018
A Nyquist rate SAR ADC employing incremental ΣΔ DAC achieving peak SFDR = 107 dB at 80 kS/s
IEEE Journal of Solid-State Circuits, Volume: 53, Issue: 5, Page s: 1493 - 1507
2018
Patents
- A. Herkle, J. Becker, M. Ortmanns
[DE] Verfahren und Vorrichtung zur Erzeugung einer digitalen Signatur
DE102016204055A1, Patent record available from the German Patent
2016