Room: 43.2.409
Tel.: +49 (0)731 50 26214
michael.pietzko(at)uni-ulm.de
M.Sc. Michael Pietzko
I studied electrical engineering at Saarland University, where I received my B.Sc. degree in October 2016. I continued my studies at the University of Ulm, where I received my M.Sc. degree in January 2020. From October 2018 to March 2019, I worked as an intern in the ASIC Design group at the Robert Bosch Research and Technology Center (Sunnyvale, CA). The topic of my Master thesis was ''Highly Linear Gm-C based Sigma Delta Modulator''.
In February 2020 I started working towards my Ph.D. degree at the Institute of Microelectronics at the University of Ulm under the supervision of Prof. Dr.-Ing. Maurits Ortmanns. My current research interest is in the field of ultra-low power continuous-time Sigma-Delta analog-to-digital converters.
Student theses
[rp] = Bachelor thesis, [mt] = Master thesis
Past theses
- Sherif Elsayed
Calibration of High-Speed Time-Interleaved ADCs[mt] - Mohamed Mahmoud
Investigation of Time-Interleaving in Noise-Shaped SAR ADCs[mt] - Julian Spiess
Power Efficient Delta-Sigma Modulator with Bitwise ELD Compensation[mt]
Publications
2024
A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI
IEEE International Symposium on Circuits and Systems (ISCAS), Singapore
May 2024
DOI: | 10.1109/ISCAS58744.2024.10558087 |
2023
A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI
ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
September 2023
DOI: | 10.1109/ESSCIRC59616.2023.10268704 |
Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators
21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom
June 2023
DOI: | 10.1109/NEWCAS57931.2023.10198050 |
Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers
IEEE Transactions on Circuits and Systems I: Regular Papers
May 2023
DOI: | 10.1109/TCSI.2023.3269573 |
2022
Bitwise ELD Compensation in ∆Σ Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, USA
May 2022
DOI: | 10.1109/ISCAS48785.2022.9937305 |
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA
May 2022
DOI: | 10.1109/ISCAS48785.2022.9937739 |
2021
FIR filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
May 2021
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (Online)
May 2021